The re-use of circuit designs has become an important trend in the integrated circuit design industry. Companies may exchange or license design intellectual property (or “design IP”), typically including schematic and layout information for commonly used circuit blocks. The creation of a new integrated circuit may thus be greatly simplified by assembling pre-designed circuit blocks into a nearly complete system, with minimal new design effort required.
Verification is an important step in the process of designing and creating an electronic product. Verification helps ensure that the electronic design will work for its intended purpose, and is usually performed at several stages of the electronic design process. Circuit designers and verification engineers use different methods and analysis tools to verify circuit designs, including simulation. Simulation verifies a design by monitoring computed behaviors of the design with respect to test stimuli. Circuit performance measurements may be performed by a post-simulation engine that evaluates simulated circuit waveforms. A variety of commercially offered software programs are available for circuit simulation.
Digital and mixed-signal simulators support a concept known as a verification unit or “vunit”′ in Property Specification Language (PSL) (or the System Verilog Assertions (SVA) “bindfile” equivalent). Verification units are containers of properties that describe the verification requirements of a circuit design. Verification units in the verification domain are thus rather analogous to modules or subcircuits, which are used to capture design information in the design domain. Verification units however capture verification information in a standalone entity or separate file from the circuit design itself. During simulation, the contents of a verification unit may be considered alongside corresponding modules or subcircuits of a circuit design, sometimes on a per-instance basis.
Recent additions to analog circuit design products have enabled users to enter analog PSL assertions and store them in a design suite alongside their circuit schematics. Writing PSL/SVA assertions does not however come naturally to many modern analog design tool users, given the text-based pedigree of these assertion languages. Most analog designers may instead prefer to use a graphical user interface (GUI) to point and click from a library of pre-written assertions.
Since analog assertion management tools are relatively new, such “publication for re-use” flows and interactive use models do not yet exist. Thus there is a need for an improved approach to managing assertion-related information. Accordingly, the inventors have developed a novel way to help circuit designers both publish and re-use assertion-related information for analog and mixed-signal circuit designs.